Reconfigureable system architecture

ABSTRACT

Reconfigurable signal processing architecture includes a reconfigurable data processing module in which data is input to the module in a packet frame structure including configuration frames and processing frames. Each frame includes a header having at least one mode selection bit indicating whether the frame contains reconfiguration data or processing data. The module is operable in a reconfiguration mode or a processing mode according to the content of the frame header.

The present invention relates to reconfigurable system architecture. Ithas been designed for digital radio transmitters and receivers inparticular but has many other potential applications.

BACKGROUND

FIG. 1 is a diagram of a generic digital radio transceiver having ananalogue processing Section 2 and a digital processing Section 3. Aradio frequency (RF) signal is radiated/intercepted by an antenna 4 andsubsequently filtered, amplified, and upconverted/downconverted to anintermediate frequency (IF) in the analogue processing Section 2. Thesignal is converted to analogue/digital signals using the D/A and A/Dblocks (5, 6). The digital front-end block 7 performs DigitalUp/Downconversion and sample rate conversion of the digital signals. TheBaseband DSP block 8 performs all the data processing necessary toprepare the signal for transmission/reception. All of the foregoing isdone in real time.

The digital front end 7 is implemented on hardware due to thecomputational complexity and has a fixed structure. Reconfigurablehardware for example FPGAs (field programmable gate arrays) can be usedto implement the digital front end 7 to provide more flexibility &reconfiguration.

The DSP baseband algorithms are stored in non-volatile memory and areloaded into the DSP from program memory 9 at run-time. To modify the DSPoperation new programs can be loaded into memory 9 offline with aspecific reconfiguration protocol.

The use of reconfigurable architectures is gaining an important role inthe system-on-a-chip design platforms. Applying reconfigurablearchitecture to implement not only the dataflow intensive computationsbut also the control oriented computation (Layer 1, Layer 2 or Layer 3software for network protocol processing) or data stream basedcomputation (e.g. data routing, shuffling and interleaving) is a verypromising approach.

FIG. 2 shows the basic recongurable architecture model whereconfigurations for DSPs and FPGAs, one of each which is indicated by 11,12, are previously downloaded to the configuration memory 13. The basicarchitecture model of DSP typically includes data memory 16, functionalunit 17, controller 18 and instruction memory 19. An FPGA typicallyincludes a configurable logic block (CLB) 20 including look up table 21and switch matrix including switch box 22. A configuration controller 14loads the selected configuration to DSP program memory 16 or FPGAdistributed SRAM that realizes the logic functions and routing betweenlogic blocks. The choice of configuration is controlled by configurationselect logic 15.

The reconfigurable software still takes up a large portion of theresultant cycle/energy even though optimizations can reduce the costsignificantly. Part of the reason is that the configuration is done viaa microprocessor. One potential optimization is to have a dedicatedconfiguration code generator or DMA to take care of the configurationdata movements.

Reconfigurable systems are usually formed with a combination ofreconfigurable logic and a general-purpose microprocessor. The processorperforms the operations that cannot be done efficiently in thereconfigurable logic, such as data dependent control and possibly memoryaccesses, while the computational cores are mapped to the reconfigurablehardware. This reconfigurable logic can be supported either bycommercial FPGAs or by custom configurable hardware.

An example of a reconfigurable processor is the Chameleon SystemsReconfigurable Communication Processor (RCP). The RCP provides aplatform-based approach that incorporates three core architecturaltechnologies: a complete 32-bit embedded processor subsystem, ahigh-performance 32-bit reconfigurable processing fabric, andeConfigurable Technology. The RCP architecture disclosed in U.S. Pat.No. 6,288,566.

In this architecture, a configuration bit stream is stored in the mainmemory. It is loaded onto the fabric at runtime by DMA. Eachreconfigurable fabric slice has two planes for bit streams. An activeplane executes the working bit stream and a back plane contains the nextconfiguration bit stream. Switching from the back plane to the activeone takes one cycle. Therefore, the back plane can be effectively usedas cache for loading configuration.

The RCP is targeted for 3G wireless basestations and not suitable forlow power devices. Traditional approaches implement each of the fourchip-rate processing algorithms as separate hardware modules in ASICs orFPGAs.

The present invention aims to achieve a number of desirablecharacteristics in a reconfigurable architecture.

The desirable characteristics are:

-   -   Run-time reconfigurabilty of the digital processing section    -   Method of reconfiguration control using data packets    -   Data processing and reconfiguration synchronisation    -   Energy efficient implementation for low power devices

A power efficient design relies on the integration of algorithmdevelopments and architecture design to exploit the full potential ofcommunications theoretical results and advanced technology.

It would therefore be advantageous to perform algorithm level selectionsand modifications based on efficient implementation criteria, which canlead to vastly reduced processing requirements without systemperformance degradation. Architectures would be needed to match thecomputational requirements of the signal processing algorithm(filtering, coding, equalization, etc), which can lead to vastly reducedimplementation cost and energy consumption and at the same timeproviding sufficient flexibility.

The patent invention provides reconfigurable signal processingarchitecture including a reconfigurable data processing module in whichdata is input to the module in a packet frame structure includingconfiguration frames and processing frames, each frame including aheader having at least one mode selection bit indicating whether theframe contains reconfiguration data or processing data, and in which themodule is operable in a reconfiguration mode or a processing modeaccording to the content of the frame header and mode selection bits areseparated from data in each frame and used to control mode selectionlogic in the module determining how incoming data is handled.

Thus, in contrast to prior art such as that shown in FIG. 2 in whichconfiguration data is input to a reconfigurable module separately fromdata to be processed, in the present invention the reconfigurable modulereceives configuration data in the same packet frame structure as thereal time processing data.

It will be appreciated that this single module structure can be extendedto include several similar modules.

The preferred solution presented is thus a modular implementationapproach, which preserves the structures of signal processing block toestablish connections between algorithm, architecture and physical levelfor high predictability and quick feedback, and increases productivitythrough reusing building blocks.

A direct mapped approach and a predetermined module library are centricto this approach, where each coarse gain function of the algorithmimplementing the signal processing block is mapped to a highly optimizeddedicated hardware. Having done this it is possible to estimate changesin performance, power and area resulting from any reconfiguration usingcomputer modeling.

An embodiment of the invention will now be described by way of exampleonly and with reference to the accompanying drawings in which:

FIG. 1 is a schematic block diagram of a generic digital transceiver;

FIG. 2 is a schematic block diagram of a basic reconfigurablearchitecture model;

FIG. 3 is a schematic block diagram of a reconfigurable digitalprocessing architecture according to the invention;

FIG. 4 shows the architecture of FIG. 3 extended to a plurality ofreconfigurable processing modules; and

FIG. 5 shows an example of the architecture of FIG. 4 used for thespecific application of adaptive modulation.

A novel modular reconfigurable architecture & method of reconfigurationis now described. The purpose is to allow run-time reconfiguration ofthe real-time digital processing section of the digital radio. Theproposed architecture can be realized in software or hardware dependingon the computational complexity, power requirements of the system.

FIG. 3 shows the basic structure of the solution. A reconfigurableprocessing module 25 is driven by a packet frame structure generallyindicated at 26 that provides the data to be processed by the module andreconfiguration data in a data section 27. The header 28 contains thecontrol bits that determine the mode of operation of the processingmodule 25. The module receives mode selection data from decoded block 29and includes mode select 30, configurable registers 31 and processingblock 32. Data is supplied to mode select block 30 via buffer 33.

The module can operate in 3 modes.

-   1) Bypass mode effectively switching off the module 25, that is the    module passes the data without modification-   2) Process mode where data provided by the packet is processed by    the processing block 32.-   3) Reconfiguration mode where the data in the frame contains    reconfiguration parameters for the config. registers 31 to modify    the operation of the processing block 32. The connection between the    config registers and the processing block is wide enough to ensure    real-time reconfiguration.

The configuration parameters are stored in Flash memory 34 which can bealso loaded as the default parameters for future operation.

The decode block 29 decodes the header to determine the mode ofoperation to drive the select block 30. As a result, a separate controlsignal from a separate control channel is not necessary. The bufferblock 33 stores the data until the header 28 is decoded and processingblock 32 is ready for the data.

The common frame structure for delivering user data and configurationdata simplifies the operation by avoiding the synchronisation problemrequired when data and control information are sent separately to thesystem as in the example of FIG. 2. The size of the data field isvariable and is determined by the digital radio system or otherapplication implemented.

Differences in data rates between frame delivery, and rate of operationof the configurable register 31 and processor 32 are accommodated by thebuffer 33 which acts as rate adaptor.

For example, it may be necessary to buffer several frames for a completereconfiguration of configuration register 31. Similarly buffer 33assists in rate adaptation if the frame rate is different from theprocessor rate.

With one module, only two mode selection bits are needed. For example,the first of the two bits may indicate by pass mode, the secondconfiguration mode and two nulls processing mode, as indicated in thetable below: 1 X Bypass 0 0 Process 0 1 Reconfigure

Depending on the mode the select block 30 passes data to theconfiguration registers 31, processing block 32 or straight to theoutput.

The effective mode switching between recinfiguration and processingtakes no time because the processing and reconfiguration data are in thesame frame structure.

A further embodiment of the architecture is shown in FIG. 4 in whichlike parts in FIG. 3 have like numerals. The structure contains N numberof processing blocks 32 that can implement a chain of modules 25 thatcan be reconfigured as required to implement a flexible digital radio.The header 38 is extended to 2N bits to provide separate control foreach processing block 25. An extended decoder 39 serves all of themodules as does an extended flash memory 44.

The reconfiguration data contained in the frame can be used for one ofthe blocks or all. In this case the length of the data field 37 can beN*M bits.

The modules need not necessarily be in series. FIG. 3 could be extendedto include parallel modules. In that case the header and the decoderwould need to handle an address field for module identification.

The entire digital radio processing section of a radio transceiver canbe implemented using this architecture. A digital IF section can beimplemented on reconfigurable hardware using this architecture wherefilter parameters can be easily updated at run-time.

For the baseband section FIG. 5 is an example of a reconfigurablemodulation architecture where a number of modulation schemes from singleto multicarrier modulation schemes can be implemented using FPGAs, DSPsor a combination. The blocks can be combined and controlled using themultimode structure of the invention.

FIG. 5 shows serial parallel convertor 50 receiving data fortransmission on the transmitter side mirrored by parallel/serialconverter 51 on the receiver side, constellation mapping 52, de-mapping53, spreading controller 54, and corresponding Rake combiner 55, pulseshapers 56, 57 and multi-carrier modulation and de-modulation 58, 59. Ina modular system of this kind, configuration controller 60 would controlparameters for the respective pairs of the modules such as framing(block 61) array mapping (block 62), spreading codes (block 63), filtercoefficients (block 64) and sub-carrier frequencies (block 65).

The packet based data structure also has an advantage for implementingmodulation schemes that are adaptive according to the quality of thecommunication channel. A configuration data frame can be formed toreconfigure the transmitter to a more suitable modulation scheme as soonas the received packet is processed by the receiver, thus maintaining agood quality connection. This is a major requirement for all futuregeneration communication systems.

The structure in FIG. 5 can be implemented using the arrangement shownin FIG. 3 where each block can be mapped to a reconfigurable processingmodule.

Other baseband blocks can also be incorporated such as channel codingand equalisation to implement a complete system that can be configuredto any communication standard.

1. Reconfigurable signal processing architecture comprising areconfigurable data processing module in which data is input to themodule in a packet frame structure including configuration frames andprocessing frames, each frame including a header having at least onemode selection bit indicating whether the frame contains reconfigurationdata or processing data, and wherein the module is operable in areconfiguration mode or a processing mode responsive to of the frameheader and the mode selection bits are separated from the data in eachframe and are used to control mode selection logic in the module fordetermining how incoming data is handled.
 2. Architecture as claimed inclaim 1 comprising a plurality of reconfigurable data processing moduleseach of which receives data in said packet frame structure and each ofwhich is operable in a reconfiguration mode or a processing modeaccording to the frame header.
 3. Architecture as claimed in claim 2 inwhich the frame header contains at least one mode selection bit for eachof the modules.
 4. Architecture as claimed in claim 3 in which the modeselection bits are decoded by a single decoder serving a plurality ofmodules.
 5. Architecture as claimed in claim 4 in which the decoded modeselection data is supplied to the modules in parallel.
 6. Architectureas claimed in claim 2 in which the modules are connected to each otherin series.
 7. Architecture as claimed in claim 1 in which at least oneof the modules is additionally operable in a bypass mode in whichincoming data is not acted on by the module and in which the headeradditionally indicates whether or not the module is to act on the data.8. A radio signal processing apparatus in which signals are processeddigitally, in which at least some components of the digital processingsection of the apparatus are configurable and incorporate architectureas claimed in claim
 1. 9. Architecture as claimed in claim 1 in whichdefault up configuration data is supplied to the at least one modulefrom memory outside the at least one module.
 10. A radio signalprocessing apparatus according to claim 8 wherein the apparatus isselected from a group consisting of a receiver, a transmitter or atransceiver.
 11. Architecture as claimed in claim 1 including aplurality of said reconfigurable data processing modules wherein each ofthe modules is configured to be operated in a bypass mode in whichincoming data is not acted on by the module and in which the frameheader additionally indicates whether or not the module is to act on thedata.